The present invention relates to a semiconductor device having the function of storing information therein on a non-volatile basis, and particularly to a semiconductor device having nonvolatile memory cells each storing information therein on a non-volatile basis according to the amount of an electrical charge accumulated in a charge storage layer such as a floating gate. More specifically, the present invention relates to a configuration for performing data access in parallel during an erase operation mode.
A flash memory is of a memory which stores information therein on a non-volatile basis. The flash memory has been widely used for the storage of boot program information to a processor and the storage of an application data/program such as download data to a portable device, etc.
A mixed flash memory built in a microcomputer normally has a memory size which ranges from a few KB (K bytes) to a few hundred KB. When an erase operation is carried out in a normal NOR-type flash memory cell, it is necessary to apply −10V to a control gate thereof and apply 10V to a substrate region. This substrate erase voltage is transferred to source and bit lines through source and drain regions of a memory cell transistor. Thus, upon a verify operation for confirming an erase state of the memory cell, there is a need to reset each region to an initial state for the execution of verify reading, and erase verify is performed after a predetermined time has elapsed from the stop of the supply of the erase voltage. A problem therefore arises in that the erase operation becomes long.
As the flash memory, there is known a memory in which a background operation mode (BGO mode) for performing data read access on another memory bank while an erase operation is being performed on one memory bank is supported. The flash memory equipped with the BGO mode however needs a plurality of banks. A small-scale memory like the mixed flash memory built in the microcomputer is accompanied by a problem that its area increases due to plural bank configurations and the area of the microcomputer increases correspondingly.
There is known a flash memory equipped with a suspend mode in order to improve access efficiency in an erase mode. In the suspend mode, an erase operation is temporarily stopped to perform data reading (external access). After the completion of this read operation, the stopped erase operation is resumed again. Therefore, a control circuit for temporarily stopping the erase operation is required and hence a problem arises in that the area of the control circuit increases. A problem also arises in that the time necessary for erasure becomes long because the erase operation is stopped.
Such a configuration that erase gates are caused to extend in a word line (memory cell row) direction and separated every block, and erasure is performed in block units, has been shown in a patent document 1 (Japanese Unexamined Patent Publication No. Hei 1 (1989)-91395). In a nonvolatile memory cell shown in the patent document 1, a positive high voltage of, for example, 27V is applied to its erase gate upon an erase operation. A bit line, a source line and a control gate thereof are set to 0V. Thus, electrons are pulled out from a floating gate thereof to the erase gate so that the floating gate is positively charged. At data writing, the control gate is set to a positive high voltage of, for example, 21V, the drain is set to 10V, the source is set to 0V, and the control gate is set to, for example, 5V. Thus, hot electrons are generated in the neighborhood of the drain, so that high-energy electrons generated by impact ionization thereof are injected into the floating gate. An erase gate line is coupled in common to erase lines within each block and erasure can hence be performed in block units. Thus, the patent document 1 can realize the shortening of erase time.
Such a configuration that an erase gate is formed by an impurity layer to reduce the size of a memory cell has been shown in a patent document 2 (Japanese Unexamined Patent Publication No. 2008-270708). In the configuration shown in the patent document 2, a first program line, a first erase line and a first word line are disposed in a first direction. The first program line is coupled to a program gate (impurity region) of the memory cell. The first erase line is coupled to an erase gate (impurity region) thereof. The first word line is coupled to a word line node (control gate) thereof. In the patent document 2, an impurity layer that configures the erase gate is placed between an impurity region that configures a program gate line and an impurity region coupled to a bit line. The erase gate line and the program line are arranged in the same direction to thereby allow the impurity region of the erase gate to be shared for each adjacent memory cell in the same row, thus making it possible to reduce a memory cell size. Further, the erase line and the program line are arranged in the same direction to thereby limit a program operation and an erase operation to one page (word line), thus making it possible to suppress the occurrence of program disturbance with respect to another page.